1. Field of the Invention
The present invention relates to a boosted clock generator, and more particularly to a boosted clock generator having an N-type metal-oxide-semiconductor field effect transistor (NMOSFET), which is taken as a pass gate transistor.
2. Description of the Prior Art
Flash memory has become a popular non-volatile memory product in recent years, and is usually used in many computer peripheral devices that have a requirement of non-volatile memory. Generally, a high voltage, i.e. about 9 volts, is necessary to charge a floating gate of a flash memory unit while data is written into the flash memory unit. However, the voltage level of the power supply is usually less than the high voltage, so a circuit designer of the flash memory usually uses a charge pump circuit to pull up the voltage level of the power supply to a proper voltage level so as to charge the floating gate of the flash memory unit. The charge pump circuit uses a clock signal to control a switch to charge and discharge a capacitor repeatedly until the direct current (DC) voltage of the output signal of the charge pump circuit reaches the high voltage. Therefore, the amplitude of the clock signal, which is used to control the switch, deeply influences the efficiency of the charge pump circuit and the maximum voltage of a boosted signal of the charge pump circuit. Moreover, low-power circuits are becoming more and more popular and result in the decrease of the power supply voltage, so it becomes more difficult to pull the power supply voltage to the high voltage. Therefore, how to generate a clock signal having greater voltage amplitude to improve the efficiency of the charge pump circuit and the maximum voltage of the boosted signal has become a major subject of the flash memory research and design. Please refer to FIG. 1. FIG. 1 indicates the relationship between the clock signal, charge pump circuit, and the high voltage, which were described above.
Please refer to FIG. 2, which is a circuit diagram of a boosted clock generator 10 according to the prior art. The boosted clock generator 10 is used to generate a boosted clock signal, which has an amplitude greater than the rail-to-rail amplitude of the power supply voltage. The boosted clock generator 10 comprises a clock generator 12 for generating a first clock signal PH and a first complementation clock signal PHB that is complementary to the first clock signal PH, a cross-coupled boost circuit 14 electrically connected to the clock generator 12 for boosting the first clock signal PH so as to generate a second clock signal CPH and a second complementation clock signal CPHB that is complementary to the second clock signal CPH, and a bootstrap pass gate 16 electrically connected to the cross-coupled boost circuit 14 for passing a higher voltage of the second clock signal CPH. The first clock signal PH and the second clock signal CPH are inphase, and the first complementation clock signal PHB and the second complementation clock signal CPHB are inphase. The bootstrap pass gate 16 comprises a pass gate transistor 18, which is a P-type metal-oxide-semiconductor field effect transistor (PMOSFET). The drain of the pass gate transistor 18 is electrically connected to the cross-coupled boost circuit 14 so as to output the second clock signal CPH, and the source of the pass gate transistor 18 is electrically connected to an output terminal COUT of the boosted clock generator 10 so as to pass the higher voltage of the second clock signal CPH. The bootstrap pass gate 16 further comprises a discharge transistor 20, which is an N-type metal-oxide-semiconductor field effect transistor (NMOSFET), electrically connected to the output terminal COUT and a grounding terminal for transmitting a grounding voltage GND. The gate of the pass gate transistor 18 and the gate of the discharge transistor 20 are electrically connected to the terminal that outputs the first complementation clock signal PHB. When the first complementation clock signal PHB is low, the channel of the pass gate transistor 18 turns on so that the higher voltage of the second clock signal CPH is transmitted to the output terminal COUT. When the first complementation clock signal PHB is high, the channel of the discharge transistor 20 turns on so that the grounding voltage GND is transmitted to the output terminal COUT. Finally, the boosted clock signal is generated.
Generally, the clock generator 12 is a non-overlap clock generator and comprises two cross-coupled NAND gates 22 and 24, an inverter 26, and two buffers 28 and 30 as shown in FIG. 2. The two buffers 28 and 30 are two inverters. The clock generator 12 is used to generate the first clock signal PH and the first complementation clock signal PHB according to the clock signal CLK. The cross-coupled boost circuit 14 usually comprises a cross-coupled pair, which is composed of two NMOSFETs 32 and 34 and two boost capacitors 36 and 38 as shown in FIG. 2. The drain of one of the two boost capacitors 36 or 38 may be coupled to the source of the other boost capacitor 38 or 36. The cross-coupled boost circuit 14 uses the first clock signal PH and the first complementation clock signal PHB to charge the two boost capacitors 36 and 38 repeatedly so as to boost the second clock signal CPH and the second complementation clock signal CPHB. The cross-coupled boost circuit 14 further comprises an activating module, which is composed of two NMOSFETs 40 and 42, electrically connected to the two output terminals of the cross-coupled boost circuit 14 for applying an activating voltage to the two output terminals of the cross-coupled boost circuit 14 to activate the cross-coupled boost circuit 14.
However, because the pass gate transistor 18 of the bootstrap pass gate 16 is a PMOSFET, a latch-up phenomenon may occur and results in errors or a breakdown of the boosted clock generator 10. To avoid the latch-up phenomenon, the circuit designer usually electrically connects the N substrate (or N-well) of the pass gate transistor 18 with a DC voltage source of the boosted clock generator 10 that has the highest voltage level. However, the voltage level of the second clock signal CPH may be double the voltage level of the power supply, i.e. 2 Vdd, so the DC voltage source cannot be less than 2 Vdd. Otherwise, the latch-up phenomenon may occur. The design of the DC voltage source, thus, is a great challenge for the circuit designers. Another circuit design for avoiding the latch-up phenomenon is electrically connecting the substrate of the pass gate transistor 18 with the source of the pass gate transistor 18. Theoretically, because the P type source and the N type substrate have the same voltage level at any time, no forward bias of the PN junction will occur so that the latch-up phenomenon can be avoided. However, the pass gate transistor 18 actually may have structural difference, which results in the equivalent resistance of the drain not being equal to the equivalent resistance of the substrate, so the transient forward bias of the PN junction may occur and lead to the latch-up phenomenon.
It is therefore a primary objective of the claimed invention to provide a pass gate transistor having an NMOSFET to avoid the latch-up phenomenon of the PMOSFET pass gate transistor of the prior art.
Briefly summarized, the claimed invention discloses a boosted clock generator for generating a boosted clock signal. The boosted clock generator comprises a clock generator for generating a first clock signal, a cross-coupled boost circuit electrically connected to the clock generator for boosting the first clock signal so as to generate a second clock signal, a bootstrap pass gate having an NMOSFET pass gate transistor, electrically connected to the cross-coupled boost circuit for passing a higher voltage of the second clock signal, and a level shift circuit electrically connected to the bootstrap pass gate for generating the boosted clock signal according to the higher voltage of the second clock signal.
The claimed boosted clock generator uses an NMOSFET as the pass gate transistor, to avoid the latch-up phenomenon of the prior art pass gate transistor, i.e. a PMOSFET, and uses a the level shift circuit to replace the prior art discharge transistor.
These and other objectives and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.